An integrated circuit ("IC") designer must consider numerous transistor attributes, such as channel length and doping concentration, in modeling or predicting semiconductor behavior or operation. Often, an IC designer must balance conflicting transistor attributes in achieving desired semiconductor behavior, such as a specified drain-to-source current vs. drain-to-source voltage curve ("I/V curve"). For example, in order to improve transistor speed, an IC designer may increase current drive and thus speed up the charge and discharge of capacitive loads. This generally requires shorter channel lengths and a thin gate oxide thickness. Similarly, an IC designer may desire to shorten channel lengths to minimize the size of the semiconductor device. However, shorter channel lengths may cause a drop in threshold voltage, among other problems, all of which lead to undesirable higher leakage current.
Various semiconductor device simulators have been built to model designed transistor behavior. Device simulators, such as PISCES, Medici, Suprem3, Suprem4, PdFad, and MINIMOS have been developed to emulate semiconductor behavior based upon specified transistor attributes, such as doping concentration, channel length, gate oxide thickness, junction depth and so on.
FIG. 1 illustrates a prior art method for modeling an integrated circuit, and in particular to obtain I/V curves for a transistor having specified attributes as illustrated in FIG. 2. FIG. 2 illustrates an n-channel metal oxide semiconductor ("NMOS") device 200 formed on a substrate 201. NMOS device 200 may be part of a complementary metal oxide semiconductor ("CMOS") device. Device 200 includes, among other specified transistor attributes, a specified channel length L, doping concentration N+ in a respective source and drain, and gate oxide thickness T. Only a few of the numerous transistor attributes typically found in a semiconductor device are illustrated in FIG. 2.
Before an accurate model of NMOS device 200 may be obtained, certain "parameters" must be extracted from the device 200, as illustrated in FIG. 1. Typically, a device simulator requires specific device "parameters" in order to provide a simulation. For example, the semiconductor device simulator may require five specific sets of parameters as illustrated by parameters 103-107. Some of the parameters are extracted from a device parameter extractor 102. Some of these parameters may correspond to physical measurements of the device 200, such as channel length L and doping concentration N+, while other parameters may be based on or derived from these physical measurements or other parameters.
Device parameter extractor 102 may include a personal computer and a signal analyzer coupled to a probe station for measuring signals from the device 200. The signals may include drain-to-source current, I.sub.DS, drain-to-source voltage V.sub.DS and gate voltage V.sub.G measurements. Parameters associated with the single semiconductor device 200 or multiple semiconductor devices 200 having varying attributes, such as a shorter channel length and higher doping concentration, may be extracted by device parameter extractor 102.
The five sets of parameters 103-107 illustrate parameters associated with a particular semiconductor device, for example, a CMOS device. Parameters 105, shown as .alpha..sub.1 TT, .alpha..sub.2 TT . . . , represent parameters associated with a typically nominal target-manufactured CMOS device having predetermined attributes and assuming minimum process variations. Parameters 103, shown as .alpha..sub.1 FF, .alpha..sub.2 FF, . . . , represent parameters associated with a CMOS device which is manufactured under process conditions which result in a CMOS device which operates at switching speed extremes. In other words, the CMOS device attributes are manufactured under conditions which create a fast NMOS device and fast PMOS device. Parameters 103 are derived from parameter 105. Parameters 104, shown as .alpha..sub.1 FS, .alpha..sub.2 FS . . . , illustrate parameters associated with a CMOS device where the NMOS device is manufactured under process conditions which enable maximum switching speeds while the PMOS device operates at minimum operating switching speeds. Parameters 104 are also derived from parameter 105. Likewise, parameters 106, shown as .alpha..sub.1 SF, .alpha..sub.2 SF . . . , refer to a manufactured CMOS device in which the NMOS device operates at a minimum switching speed and the PMOS device is manufactured under conditions which enable operations at a maximum switching speed. Finally, parameters 107, shown as .alpha..sub.1 SS, .alpha..sub.2 SS . . . , refer to a manufactured CMOS device in which both the NMOS device and PMOS device are manufactured under conditions which create minimum switching speeds for both devices. These five process parameters 103-107 are also referred to as the "five corners" or illustrate the operational or behavioral envelope for a typical manufactured CMOS device. The five corners are shown by reference numeral 110. Based on these measured and derived parameters 103-107, designers can model, with a semiconductor simulator 108, the IN curve 109 of a semiconductor device. In particular, the designer can determine worst-case I/V curves 109a-b and how worst case transistors affect a circuit.
The prior art method described above suffers from many disadvantages in accurately modeling a transistor. First, because the parameters 103-107 do not accurately reflect mass-produced semiconductor devices under typical process conditions, the I/V curve 109 and five corners 110 do not reflect realistic worst-case I/V curves and device operating envelopes, respectively. Specifically, parameter 103, representing a fast PMOS device and fast NMOS device, does not accurately represent a mass-produced CMOS semiconductor device. For example, the doping concentrations necessary to create a CMOS semiconductor device corresponding to these parameters would rarely, if at all, be encountered in a mass production line. Likewise, parameters 107 do not accurately reflect the worst-case slow NMOS device and slow PMOS device typically manufactured in a production line. Thus, the I/V curves 109a-b and five corners 110 do not accurately represent the worst-case semiconductor devices manufactured on a typical mass-production line. A designer is typically factoring in unnecessary manufacturing tolerances, or bands, in designing a semiconductor device based upon exaggerated worst-case curves. Unnecessary spacing may be designed into semiconductor components, creating slower and larger devices than could otherwise be manufactured. Thus, such conventional techniques may result in "over-designing" such semiconductor devices.
Second, prior methods of modeling semiconductor devices do not use semiconductor manufacturing process simulations generating distributions of manufactured semiconductor devices, thereby improving the accuracy of a semiconductor simulator. Specifically, conventional methods use parameters derived from a single or few semiconductor devices. These parameters do not accurately reflect the substantial variations in semiconductor manufacturing process steps and how these variations affect a mass-produced semiconductor device behavior. For example, the prior method does not consider how manufacturing variations in forming oxidation layers or channel lengths affect modeled semiconductor devices.
Third, the prior method generally does not improve as further information regarding the manufacturing of the mass-produced semiconductor device is obtained. Specifically, only a relatively small number of values in parameters 105 are measured and used to derive parameters 103, 104, 106 and 107. Thus, greater information regarding the semiconductor device manufacturing process does not improve semiconductor simulation results. The prior method does not generate an improved semiconductor device model if improved information regarding the distribution of mass-produced semiconductor devices from a modeled production line is known. In this sense, the prior method is not adaptive.
Thus, there is a need in the art for a parameter extraction apparatus, method, and system which take into account intra-field variations in order to obtain more realistic worst case curves. In addition, it would be desirable to have such a parameter extraction apparatus, method, and system be able to extract parameters even for a new generation technology where empirical data is not readily available.